1. Technical field
The invention relates to combinational logic. More particularly, the invention relates to overlapping logic for data and enable inputs to a logic function.
2. Description of the Prior Art
Application specific integrated circuit (ASIC) is a designation applied to a variety of devices fabricated in a variety of semiconductor technologies. An ASIC is designed to perform a specific function. The major advantages of ASICs are typically lower unit cost and higher performance. This is the result of eliminating circuitry from the chip otherwise needed to make it programmable and incorporating only the logic functions that are needed for the application. This makes a smaller, less costly chip. Higher performance is a result of directly implementing the logic instead of using an instruction set that requires multiples of clock cycles to execute, as with a microprocessor.
ASICs can be divided into two categories: standard and custom. Standard ASICs are generally commodity items which have been designed by a semiconductor manufacturer and which are sold in large volumes. Custom ASICs are generally designed by or for a specific customer and are not available to the public. This allows the developer of a custom ASIC to exploit the advantages of the device. One disadvantage of custom ASICs is the high nonrecurring engineering cost associated with designing the ASIC.
ASICs are typically designed using a schematic entry design system which includes a library of cells that are usable by a target silicon foundry and technical data relating to cell performance that must be programmed into a schematic capture tool.
A block diagram of the desired ASIC is first created by the system designer. The design is implemented by placing logical elements from the library onto the screen of a workstation. The elements of the design are uniquely defined by an instance number, connections are drawn in, and the wires are named. The operator then runs the schematic entry program to produce a netlist. In producing the netlist, all of the positional information contained in the schematic drawing, i.e. what elements goes next to what and where the critical signal paths are, is lost. Because the netlist is produced from a schematic, there is no actual information regarding such factors as, for example stray capacitance, inductive coupling, or transmission line length. These parameters must be estimated and added to the netlist in a format that is usable by a timing simulator.
In addition to the netlist obtained from the schematic entry program, test vectors must be generated to simulate the netlist. To bridge the interface between the schematic entry program and the simulator program, the test vectors must be in a format required by the simulator. The simulator program itself must be programmed to handle all of the logic elements contained in the foundry library.
When the simulation is completed, the results must be examined. This requires a program that takes the output of the simulator and displays it in the format desired.
The next interface is that between the schematic entry program and the auto-place-and-route program. The router must be programmed with the appropriate standard cell library and the output from the schematic entry tool must be in a format acceptable to the router.
The router outputs the geometrical data that define the structures and locations of the structures used in the fabrication of the design in silicon. These structures define data paths and capacitive loading which may be critical to the performance of the circuit. Because the router may not produce performance that meets the design specification, it is necessary to run an extraction program on the output of the router. The extraction program traces the layout and constructs a netlist of the actual layout. The extractor can also calculate the actual node loading.
The extractor must be programmed with appropriate data relating to the electrical properties of the various structural layers. The extractor also must assure that the output format of the router is usable by the input to the extractor, and that the output of the extractor is usable by the input to the timing simulator. The netlist containing the actual loading obtained by extraction from the layout is referred to as back-annotated data. The timing simulation obtained from simulating the back-annotated netlist should represent the actual circuit performance. Otherwise, engineering (i.e. human) intervention is required.
The actual netlist, i.e. the netlist provided by the extractor, and the netlist provided by the schematic entry, i.e. the intended netlist, must be compared to determine if the real netlist is the same as the intended netlist. This is performed by a layout-versus-schematic program.
Many design systems are based upon the use of a Hardware Description Language, such as VHDL or Verilog, and may use a silicon compiler and synthesizer. Assuming the system is described in VHDL and partitioned, if needed, into one or more ASICs, the resulting VHDL description must be converted to a detailed specification. The specification is typically dependent upon the design system that is used to implement the design. For example, a synthesizer program that is used to synthesize the ASIC from the VHDL description must be expanded to include specified timing. To determine if the specification is correct, the VHDL description must be simulated. Thus, test vectors described in the required stimulus format for a VHDL simulator must be provided. Once the specification is determined to be correct, a synthesizer program which contains a library of cells and a set of design rules appropriate for the target silicon foundry is run.
The HDL design tools ideally should allow the user to describe only the desired operation of the logic circuit, i.e. the signals generated by the logic circuit. However, HDL only permits an operational description of simple circuit elements. Accordingly, only designers that have knowledge of both the use and operation of logic elements and the operational features of the desired logic circuit can successfully use HDL.
B. Gregory, R. Segal, Method For Converting A Hardware Independent User Description Of A Logic Circuit Into Hardware Components, U.S. Pat. No. 5,530,841 (25 Jun. 1996) describe the generation of a logic network using a hardware independent description technique. A hardware generator is used to synthesize the logic network based upon information provided by an assignment condition generator.
In general, during the synthesis of latch logic using such systems, enable and data logic, i.e. combinational logic, overlap. It would be advantageous to simplify the overlapping logic for data and enable inputs, and thereby simplify the design. Additionally, such overlapping logic can cause timing problems after technology mapping because the same signal, i.e. the shared signal, may arrive to the data input of the latch at a different time than to the enable input of the latch. It would therefore also be advantageous to optimize circuit design in such way as to minimize or eliminate timing issues related to enable and data logic overlap.